1. Field of the Invention
This invention relates to an improved on-chip storage memory for storing variable data bits.
2. Description of the Related Art
Many memory instances are used in system on chips for storing data of variable lengths. FIFO (first in first out) or SRAM (static read/write memory) are primarily used for storing the data bits and also for high speed data buffering. Since the width of the memory is fixed and data to be stored is of variable length, memory is not efficiently utilized.
In conventional system on chips, there are number of memories utilized in the chip for data storage. The data bits may be processed by a particular block and used by either another block or their results are stored inside the chip after performing different operations. The data bits can be of different lengths. If some compression technique is used, the variation in number of bits to be stored is large.
FIGS. 1(a) and 1(b) depict two conventional methods of memory storage. FIG. 1(a) shows a method in which different memory instances (11) of different possible widths are used. Addressing is done by Virtual Address Decoding (10).
FIG. 1(b) depicts an SRAM/FIFO (12) with width equal to maximum data bits to be transferred. The data with less width is stored after 0 stuffing.
In U.S. Pat. No. 6,026,032 a dual-port, static random access memory (DPSRAM) is described as a virtual first-in-first-out (FIFO) register under the control of a microprocessor executing a stored program or similar circuit to allow both conventional random access data buffering between the data source and the data receiver and FIFO-type data buffering in which the data source and data receiver need not generate an address for each data word transferred, but these addresses may be automatically generated in sequence by the buffer using special circuitry.
It provides a high-speed data buffer for connecting a data source to a data receiver, the data buffer having a first interface receiving data from the data source and a second interface outputting the data to the data receiver. A dual port random access memory has a first port, with first address and first data lines, communicating with the first interface, and a second port, with second address and second data lines, communicating with the second interface. First address counter circuitry communicates with the first address lines to accept a first starting address and increment the first starting address applied to the first address lines as data is received from the first interface. Second address counter circuitry communicates with the second address lines to accept a second starting address and increment the second starting address applied to the second address lines as data is transmitted to the second interface.
This approach thus uses a virtual first-in-first-out memory along with a controller utilizing a fixed algorithm.
Also, U.S. Pat. No. 6,467,021 presents a data system having a store, a memory, a user interface and a memory controller where the memory is used to buffer all data transferred between the user interface and the store, the memory controller copying data directly between the store and the memory, whereas the memory controller re-organizes data when the data is transferred between the memory and the user interface. The arrangement described above for management of the storage of data with variable block size relies on the principles of partitioning of a data block to locate it efficiently in a storage medium and relocation of a data block to compensate for any change in size of the stored data blocks. It demands multiple random accesses to the storage medium for data block read and write operations and hence can only provide a high performance data storage system if fast memory is used for the storage device.
Therefore, although block sizes are of fixed size in a data storage system before compression but after data compression the size may vary over a very wide range. An efficient storage management arrangement must be able to cope with the dynamic nature of the block size distribution.
U.S. Pat. No. 5,703,812 describes a multi-bit data output buffer for transferring multi-bit data from a semiconductor memory device to the peripheral circuit. It includes a data input circuit for inputting at least two bit data, at least two bit data buffering circuits, each of at least two bit data buffering circuits buffering a corresponding one of at least two bit data from the data input circuit, and a bit data comparison circuit for controlling the amount of current flowing to at least two bit data buffering circuits according to logic values of at least two bit data from the data input circuit. The multi-bit data output buffer is capable of minimizing the generation of noise in the output data and enhancing a response speed of the output data with respect to the input data.
U.S. Pat. No. 5,761,478 relates to an arrangement for interfacing a microprocessor with a memory external thereto wherein the data size and the width of the interface both may vary.
A memory interface unit for coupling a microprocessor to a memory external to the microprocessor is described, the memory being utilized for the storage of data therein and the retrieval of data therefrom, and the memory being provided in one or more memory banks, each of the banks being provided with a set of address lines and a byte enable line, data being transferring to and from each of the memory banks on a group of data lines. The memory banks are provided in one or more banks whereby the group or groups of data lines, as the case may be, provide a memory data path having a physical transfer width for transfer of data to and from the memory, and the data being stored and retrieved over the memory data path in two or more data types, each type having a different size. The memory interface unit is provided with a set of address pins and a set of strobe pins, and it includes a first element for providing an indication of a physical transfer width of a memory coupled to the memory interface unit.
Also included is a second element for providing an indication of a data type to be transferred to or from the memory. A third element, responsive to the first element and the second element, depending on the data type indication, provides to the address pins an address, shifted in position, with at least some of the address lines used for coupling to the address lines of the one or more banks of memory, as the case may be, and with one or more of the address pins used for activation of the byte enable line or lines, as the case may be, for data to be transferred, or, alternatively, providing to the address pins an address, unshifted in position, for coupling to the address lines of the one or more banks of memory, as the case may be, for addressing data to be transferred. Depending on the physical transfer width indication, the third element also causes one or more of the strobe pins to be used as additional address pins.
But in these methods a large portion of memory is not utilized. Since a large portion of the chip is taken by these memories, proper utilization is needed. Moreover the memory devices discussed above either use memory for dumping variable data bits or as a data buffer.